As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, it is desirable to incorporate and merge logic circuits having a variety of functions with non-volatile memory circuits within one chip. As a non-volatile memory cell, a ferroelectric random access memory (FERAM) offers high density, low power consumption, high speed, and low manufacturing cost. One advantage of the FERAM compared to a static random access memory (SRAM) and/or a dynamic random access memory (DRAM) is its significantly smaller size (about one-third to about one-fourth the size of an SRAM cell).